1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a memory device including a serial access memory (SAM) employed for a serial access of data together with a random access memory (RAM) employed for an ordinary random access of data.
In general, a semiconductor memory device used as a memory for image processing such as a frame buffer requires that a data read operation is carried out with a high speed corresponding to a display speed on an image plane of a display attachment. For example, in a display having pixels of 512.times.512, a flicker arises on the image plane unless data are read out with a cycle of approximately 48 ns. The read speed in the image memory is approximately ten times as high as that in an ordinary dynamic RAM. Also, the read of display data from the frame buffer must be carried out serially and with high speed, while the write of date into the buffer must be simultaneously carried out. In order to realize the read/write operation by means of a ordinary dynamic RAM, measures to utilize a period for retrace line or to effect a time-sharing processing by means of a special method must be taken, because no more than one input/output (I/O) port is provided on the RAM. This leads to a difficulty in improvement in the efficiency in the write or change of data.
2. Description of the Related Art
As a frame buffer meeting the above requirements, a semiconductor memory device of a so-called dual port type is known and employed which includes both a random access port for a dynamic RAM and a serial access port for a SAM.
In a known example of this kind of the semiconductor memory device, the SAM is provided between the RAM and a serial I/O terminal and includes memory cells corresponding to a single row in the RAM, and a data bus for transferring serial data is provided between the SAM and the serial I/O terminal and divided into two systems. One is a data bus allocated to bit data corresponding to odd number address in the SAM, and the other is a data bus allocated to bit data corresponding to even number addresses therein.
In this arrangement, data are transferred between the RAM and SAM with a unit of an arbitrary single row in the RAM. For example, assuming that a display is connected to the serial I/O terminal and data in the RAM are transferred to the display. The data in the RAM are first read with a unit of a single row and stored in the SAM, and then, the stored data are read as a chain of serial data beginning from a bit data corresponding to a predetermined head address and transferred via the data bus to the display. In this case, when the data transfer between the RAM and SAM is carried out, the serial data transfer between the SAM and serial I/O terminal is not carried out, and vice versa. Accordingly, when the serial data transfer is carried out, the RAM and SAM can function independently of each other, so that the write operation of data can be freely carried out in the RAM. This contributes to improvement in the efficiency in the write or change of data.
Also, in the serial data transfer operation, each of bit data output from the SAM is read alternately on a first data bus for odd number addresses and a second data bus for even number addresses. Namely, when a first data bus is used in the serial data transfer, a second data bus is brought to a quiescent state, and vice versa. Accordingly, when one of the data buses participates in the serial data transfer, the other thereof can be brought to a reset state and prepared for the next participation in the serial data transfer. This contributes to a high speed read of data. As a result, a chain of serial data can be obtained without interruption at the serial I/O terminal.
However, the semiconductor memory device having the data bus divided into two systems poses a problem where the serial data transfer is carried out repeatedly with a unit of a data block of a plurality of bit data. For example, where the last address of a transfer data block and the head address of a subsequent one coincide with an odd or even number address, the respective bit data serially appears on an identical data bus and, accordingly, it becomes impossible to secure a reset period for the data bus. To prevent this disadvantage, the subsequent data block must be output with being delayed by a time period necessary for the resetting of the data bus. As a result, interruption equal to the predetermined reset period is inevitably generated between the transfer data blocks. This leads to a decrease in the read speed of data and thus is not preferable.